The present invention relates to a semiconductor design technique; and more particularly, to an exclusive OR (XOR) logic circuit for use in a semiconductor memory device.
In general, a logic circuit includes an OR logic circuit, an AND logic circuit, a NOT logic circuit, a NAND logic circuit, a NOR logic circuit and an XOR logic circuit. Since the XOR logic circuit may detect whether a logic level of an input signal is identical to that of the other input signal, the XOR logic circuit is used for a summing circuit, a subtracting circuit and a parity check circuit.
FIG. 1 is a circuit diagram illustrating a conventional XOR logic circuit.
As shown, the XOR logic circuit includes first to third PMOS transistors PM1, PM2 and PM3 and first to third NMOS transistors NM1, NM2 and NM3.
A detailed configuration of the XOR logic circuit will be described hereinafter. A source-drain path of the first PMOS transistor PM1 is coupled between a power voltage VDD terminal and the second PMOS transistor PM2. A gate of the first PMOS transistor PM1 is coupled to a first input terminal A. A source-drain path of the second PMOS transistor PM2 is coupled between a node ND and the first PMOS transistor PM1. A gate of the second PMOS transistor PM2 is coupled to a second input terminal B. A source-drain path of first NMOS transistor NM1 is formed between the node ND and the second input terminal B. A gate of the first NMOS transistor NM1 is coupled to the first input terminal A. A source-drain path of the second NMOS transistor NM2 is formed between the node ND and the first input terminal A. A gate of the second NMOS transistor NM2 is coupled to the second input terminal B. A source-drain path of the third PMOS transistor PM3 is formed between the power voltage VDD and an output terminal OUT. A gate of the third PMOS transistor PM3 is coupled to the node ND. A source-drain path of the third NMOS transistor NM3 is formed between the output terminal OUT and a ground voltage VSS terminal. A gate of the third NMOS transistor NM3 is coupled to the node ND.
The third PMOS transistor PM3 and the third NMOS transistor NM3 perform a buffering operation. A voltage level of the node ND depends on data applied to the first and second input terminals A and B. When the voltage level of the node ND is unstable, a conventional XOR logic circuit needs to perform a buffering operation.
Hereinafter, an operation of the conventional XOR logic circuit will be described in detail. In this example, data of four cases, 00, 01, 10 and 11, is applied to the first and second input terminals A and B, respectively.
First, if a logic low level LOW data is applied to the first and the second input terminals A and B, respectively, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on, and the node ND has a voltage level corresponding to the power voltage VDD. Subsequently, the third NMOS transistor NM3 is turned on and the output terminal OUT becomes a logic low level LOW due to the node ND having the high voltage level.
Second, if a logic low level LOW data is applied to the first input terminal A and a logic high level HIGH data is applied to the second input terminal B, the second NMOS transistor NM2 is turned on and the logic low level LOW data applied to the first input terminal A is transferred to the node ND through the second NMOS transistor NM2. Subsequently, the node ND has a voltage level corresponding to the logic low level LOW. And, the third PMOS transistor PM3 is turned on and the output terminal OUT becomes the logic high level HIGH due to the node ND having a low voltage level.
Third, if a logic high level HIGH is applied to the first input terminal A and a logic low level LOW is applied to the second input terminal B, the first NMOS transistor NM1 is turned on and the logic low level data applied to the second input terminal B is transferred to the node ND through the first NMOS transistor NM1. Subsequently, when the node ND has a logic low level, the third PMOS transistor PM3 is turned on and the output terminal OUT becomes a logic high level HIGH.
Fourth, if a logic high level HIGH data is applied to the first and the second input terminals A and B, respectively the first and second NMOS transistors NM1 and NM2 are turned on and the logic high level data applied to the first and second input terminals A and B are transferred to the data node ND through the first and second NMOS transistors NM1 and NM2. Subsequently, when the node ND has the logic high level, the third NMOS transistor NM3 is turned on and the output terminal OUT becomes a logic low level LOW. FIG. 2 is a waveform diagram illustrating operational waveforms of the XOR circuit shown in FIG. 1. Waveforms of the first and second input terminals A and B, the node ND and the output terminal OUT are shown in FIG. 2.
As shown in FIG. 1, data of four cases may be applied to the first and second input terminals A and B. As shown in FIG. 2, if the logic high level data applied to the first and second input terminals A and B, a noise occurs in the data. When the logic high level data is transferred to the node ND, even if the noise does not occur in the data, a voltage drop caused by a threshold voltage VTH of the first and second NMOS transistors NM1 and NM2 occurs in the node ND.
Furthermore, if the logic high level data is transferred using an NMOS transistor, a loss of the transferred data occurs. If the logic low level data is transferred using the NMOS transistor, a loss of the transferred data does not occur. On the contrary, if the logic high level data is transferred using a PMOS transistor, a loss does not occur in the transferred data. If the logic low level data is transferred, a loss occurs in the transferred data.
That is, if the logic high level HIGH data is applied to the first and second input terminals A and B, the logic high level HIGH data passes through the first and second NMOS transistor NM1 and NM2, and the data having a loss is transferred to the node ND. In other words, the node ND has a voltage level in which a voltage drop occurs from the power voltage VDD corresponding to the logic high level HIGH by the same amount as the threshold value VTH. The voltage level fails to correctly represent a predetermined data. Accordingly, in order to solve this problem, a buffering operation is performed in the node ND and the output terminal OUT obtains an output signal having a full swing between the power voltage VDD and the ground voltage VSS.
However, as shown in FIG. 2, if the noise occurs in the data, even though the buffering operation is performed, the output terminal OUT may not obtain a correct output signal.
First, if the threshold voltage VTH of the first and second NMOS transistors NM1 and NM2 is a normal value, the node ND may not to maintain a predetermined voltage level due to the noise occurring in the data, and the output terminal OUT does not maintain the predetermined output signal as well. In other words, if the logic high level HIGH data is applied to the first and second input terminals A and B, the output terminal OUT must become a logic low level LOW. But, as shown in FIG. 2, because the voltage level value of the node ND is too low, the voltage level of the node ND enables the third PMOS transistor PM3 instead of the third NMOS transistors NM3 to be coupled to the output terminal OUT, and the output terminal OUT becomes a logic high level HIGH.
To solve this problem, a transistor having a low threshold voltage is used. That is, a voltage drop of the node ND is reduced by using the threshold voltage level, which is lower than a normal threshold voltage level. And, the output terminal OUT may have a stable voltage level by using the threshold voltage level that is lower than the normal threshold voltage level. But, this still has an unstable voltage level due to the data having noise.
FIG. 3 is a circuit diagram illustrating another conventional XOR logic circuit.
As shown, XOR logic circuit includes a plurality of NMOS transistors NM1, NM2, NM3 and NM4 and a plurality of PMOS transistors PM1, PM2, PM3 and PM4.
A first PMOS transistor PM1 receives an inverted first input signal /A, and a second PMOS transistor PM2 receives a second input signal B. A third PMOS transistor PM3 receives a first input signal A, and a fourth PMOS transistor PM4 receives an inverted second input signal /B. A first NMOS transistor NM1 receives the inverted second input signal /B, and a second NMOS transistor NM2 receives the inverted first input signal /A. A third NMOS transistor NM3 receives the second input signal B, and a fourth NMOS transistor NM4 receives the first input signal A.
In this XOR logic circuit, because a power voltage VDD corresponding to a logic high level data is transferred through only the first to fourth PMOS transistors PM1, PM2, PM3 and PM4, a loss does not occur in the transferred power voltage VDD. Moreover, because the ground voltage VSS corresponding to a logic low level data is transferred through only the first to fourth NMOS transistors NM1, NM2, NM3 and NM4, a loss does not occur in the transferred ground voltage. That is, a buffering operation is performed in the node and the output terminal OUT obtains an output signal having a full swing from the power voltage VDD to the ground voltage without a loss of a threshold voltage VTH in the NMOS transistors and the PMOS transistors.
However, the XOR logic circuit shown in FIG. 3 receives the first input signal A, the inverted first input signal /A, the second input signal B and the inverted second input signal /B. That is, two inverting circuits for inverting the first and second input signals A and B are provided. If it is considered that a general inverting circuit includes one NMOS transistor and one PMOS transistor, the XOR logic circuit shown in FIG. 3 includes 12 transistors of which 4 transistors are used for the inverting circuits. Finally. The XOR logic circuit shown in FIG. 3 uses 6 transistors more than the XOR logic circuit shown in FIG. 1.
Currently, a semiconductor device has proceeded toward a low voltage, a high integration and miniaturization.
In the case of the XOR logic circuit shown in FIG. 1, the total number of transistors is small, but a malfunction may occur due to the input signal of a low voltage level and the loss of the threshold voltage value. In the case of the XOR logic circuit shown in FIG. 3, the loss of the threshold voltage value is small but the XOR logic circuit requires a large number of transistors and occupies a large area of a chip.